The present invention relates to a method for manufacturing a semiconductor device and more particularly to a method for manufacturing a semiconductor device capable of forming a high-performance BiCMOS LSI easily with a high accuracy.
Conventional semiconductor devices each comprise a bipolar transistor (hereinafter referred to simply as "Bip"), an n-channel MOS transistor (simply as "nMOS" hereinafter) and a p-channel MOS transistor (simply as "pMOS" hereinafter), as described, for example, in the Institute of Electronics, Information and Communication Engineers (IEICE) Technical Report, Integrated Circuit Devices (ICD) 87-33, 1987, (see FIG. 1).
Usually, such BiCMOS is formed as follows. First, an n-type buried layer is formed in part of a p-type substrate and subsequently a p-type epitaxial layer is allowed to grow. Then, an N well is formed in the p-type epitaxial layer, and also formed is a thick silicon dioxide film for isolation by selective implantation. Then, a gate electrode is formed, and after the deposition of an insulating film, there are formed source and drain regions of each of nMOS and pMOS by a known method. Subsequently, a base and an emitter of Bip are formed, then contact holes are formed, followed by the formation of interconnection, to complete the BiCMOS LSI shown in FIG. 1.
According to the conventional manufacturing method, as is apparent from the above explanation, first a MOS transistor is formed and thereafter a bipolar transistor is formed. In many cases, moreover, the depth of emitter, xjE(Bip), is about 0.15 .mu.m, while the depth of the source and drain regions of nMOS is about 0.20 .mu.m, and that of the source and drain regions of pMOS is about 0.35 .mu.m, thus there exists the relation of xj(CMOS) &gt; xjE(Bip) wherein xj(CMOS) represents the depth of the source and drain regions of CMOS.
The above prior art involves the problem that if the transistors are made very fine, the characteristics of the MOS transistor are deteriorated so it becomes difficult to realize a BiCMOS LSI of high integration density. Also, there has been the problem that if the transistors are attenuated while retaining the relation of xj(MOS) &gt; xjE(Bip), the characteristics of the bipolar transistor are deteriorated, thus making it impossible to realize a high-performance BiCMOS LSI.
In NIKKEI MICRODEVICES, February 1988, pp. 70-71, there are shown many BiCMOS's, in which there are included, though not many, examples of xj(CMOS) being smaller than xjB(Bip). But the details, including how to manufacture, are not shown therein at all, so it is quite uncertain whether they are practically employable or not.
Reference is also here made to IEEE Transaction on Electron Devices, Vol. 36, No. 5, May 1989, pages 890-896. In this transaction there is described a BiCMOS, in which emitter and base electrodes of Bip are formed using a two-layer polysilicon film; a gate electrode of nMOS is formed using a polysilicon film; and a gate electrode of pMOS is formed using a two-layer film comprising a titanium silicide film and a polysilicon film. If the gate electrode of pMOS formed by the two-layer film comprising a titanium silicide film and a polysilicon film is annealed at a high temperature, the boundary between the two films will be extinguished, so that the titanium silicide comes into direct contact with the gate insulating film. In this case, since the interface characteristics between the silicide and the gate insulating film is poor, such direct contact of the titanium silicide with the gate insulating film will cause leakage current to flow, leading to marked deterioration in the characteristics of pMOS. Therefore, after the formation of the titanium silicide film, it is necessary to avoid a high-temperature annealing and maintain the boundary between the above two films. To this end, in the article referred to above, after annealing at a high temperature (950.degree. C.), a titanium silicide film is formed by deposition to constitute a gate electrode of pMOS, and thereafter source and drain regions of pMOS and nMOS are formed. The emitter thickness in the bipolar transistor formed is 0.05 .mu.m, while the thickness of the source and drain regions of pMOS and nMOS are 0.2 .mu.m and 0.3 .mu.m, respectively. Thus, the source and drain thicknesses are much larger than the emitter thickness.